Design and Implementation of Millimeter Wave Frequency Multiplier in 65nm RF CMOS.

摘要

In this thesis, the design and implementation of frequency multipliers in 65nm CMOS was explored for millimeter wave oscillators and optimized to achieve higher output power and better rejection of the fundamental frequency. Several types of frequency multipliers are discussed. Transformers for AC-coupling used in the frequency multipliers were also explored. The design and optimization of the circuits was performed using Sonnet, Cadence, and ADS software tools.;In this work the design of a frequency multiplier which takes in a 12.5GHz signal and outputs 100GHz at the output is achieved. Three transformers are used for three stages of a frequency doubler to achieve a multiplication by eight. High isolation is achieved between the input frequency and the output. The output power level is -4dBm. The fundamental rejection is above 35dB. The power consumed by this frequency multiplier is 18mW. While multiplication of up to 4 is achieved in CMOS devices in other works, we are able to achieve a frequency multiplication of 8 in this work.