Combination of partial evaluation and on-the-fly code generation form an execution mode of which gains have already been demonstrated in the software field by their use in JIT (Just-in-Time) compilers. The hardware field however defers to follow, despite technological progress have done in the past years in terms of dynamic reconfiguration.;The execution modes we propose benefit from dynamic restructuring of the execution support and depend on a configurable architecture. The first challenge faced when implementing such an optimisation is the lack of tools allowing integration of these execution modes to the hardware development flow. To overcome this shortcoming, new tools have been built in the research hereby presented.;The second challenge comes from the lack of support for hardware configuration manipulation, both at the tool and documentation levels. To fill this gap, we have created a compact library allowing the adaptation of the architecture by modifying its configuration dynamically, which permits to implement new application classes. The creation of a JIT compiler proves the usability of the approach we propose, therefore opening the path to new research areas.;Keywords. Dynamic synthesis, JIT, VirtexII-Pro, bitstream, FPGA.;Such a delay in integrating those classical optimisations with respect to the software field can be explained by the important algorithmic and technological challenges underlying their deployment on a hardware architecture.
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