The limited performance improvement of transistors in ultra-deep-submicron technologies is making it more difficult to achieve computing performance increases from scaling alone. Solutions to address this challenge come from combined system-level and physical-level optimizations. At the system-level, more complex on-chip systems are implemented by integrating various processing elements with interconnections to increase parallel processing capability without the need to push transistors to high operating frequencies or advanced technologies. At the physical-level, three dimensional integrated circuits (3D-ICs) increase chip density and reduce wire delay by stacking multiple ICs vertically with through-silicon-vias (TSVs). Both techniques enlarge the system design space by introducing more design parameters such as the number of processing elements and types, interconnection topologies, IC stacking schemes, and heterogeneous technologies. Furthermore, the design parameters at different levels of abstraction interact with each other, which necessitates a system-level "pathfinding" design flow to evaluate the design parameters fast at early design stage. However, most state-of-the-art pathfinding flows focus on the register-transfer and gate levels of abstraction for system modeling and are hard to integrate with tools that focus on the transaction and instruction levels. In this work, we present a electronic system-level (ESL) pathfinding flow that integrates transaction-level and physical-level evaluation by using ESL models and interfaces, allowing fast, physically aware system design evaluation.
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