Parasitic substrate modeling for monolithic mixed analog/digital circuit design and verification.

摘要

Industry trends aimed at procuring greater levels of circuit performance have triggered a proliferation of analog and digital subsystems fabricated side-by-side on the same die. The combined requirements for both high-speed digital and high-precision analog functionality pose unique challenges to mixed-A/D circuit designers. Specifically, mono-lithic mixed-signal ICs are often characterized by parasitic analog-digital crosstalk that can cripple the operation of high-performance designs. Noise coupling through the common chip substrate has been identified as a significant contributor to this important problem.; This dissertation investigates computer-aided design (CAD) methodologies for analyzing the impact of layout-dependent, substrate-coupled switching noise in mixed-signal ICs. Since electrical-level simulation programs are frequently employed to monitor important parasitic phenomena during design verification, "substrate-aware", circuit-based modeling techniques are required to assess the noise coupling in a cognizant, quantitative fashion. In our approach, SPICE-compatible, equivalent-circuit substrate models are efficiently generated from their corresponding layout specifications using a novel application of a geometric procedure called Voronoi tessellation. The new method is applicable to virtually any substrate system, and produces models that are more accurate or simpler than those based on competing techniques.; This manuscript also discusses the implementation of the model extraction algorithms in an industry-compatible verification system called SNAPPLE (Substrate Noise Analysis Program with Post-Layout Extraction). For validation, the strategy is effectively demonstrated using several mixed-signal circuit examples.