VLSI architectures and algorithms for video coding and image processing applications.

摘要

The new era of visual communication becomes more important with the technology standard developments such as JPEG and MPEG which provides a platform that can support large, widespread global multimedia (audio, video, and data) markets. Also, a lot of image processing techniques are essential for applications, like enhancement for visual quality, and edge enhancement or blur and template matching. Of these technologies, video/image are particularly exciting in terms of multimedia applications. Current compression standards and applications for video/image and their underlying algorithms use a variety of techniques to achieve high performance, which are also the most demanding for digital signal processing power and VLSI technologies. Various architectures have been proposed to provide efficient solutions for these demands over the past few years.; In this dissertation, several VLSI architectures and algorithms which support computational requirements for real time applications are proposed. The problems studied include variable-length coding (VLC) decoder, one of the key components in current video and image coding standards. Also, multidimensional (M-D) signal processing, such as M-D transform, and M-D finite impulse response (FIR) digital filters, have been extensively studied.; A new high performance variable-length coding (VLC) decoder is proposed. It achieves higher throughput and pipeline processing by using a concurrent VLC decoding algorithm and a maximum likely bit pattern (MLBP) codebook clustering scheme. MPEG-2 experimental video data are used to simulate the performance. Highly-modular pipelined VLSI architectures for M-D transform and M-D FIR digital filters are presented. These approaches are based on a time-multiplexed computation concept. The M-D transform can be implemented by cascading time-multiplexed multiplication accumulation (TMAC) components. And, M-D convolutions can be decomposed into pipelined summations of parallel 1-D discrete convolutions, so that a modular structure is obtained. The advantages of these architectures are: (i) regular structure with high modularity, (ii) fully pipelined operation, (iii) extendible to M-D case.