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Constant resistance and capacitance models for CMOS technologies

机译:CMOS技术的恒定电阻和电容模型

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摘要

The use of constant resistance (R) and capacitance (C) models for MOSFETs in circuit and timing analysis tools can offer significant reductions in total execution time over standard circuit simulators such as SPICE, which use detailed, nonlinear MOSFET models. Two methods of determining the appropriate constant RC values for MOSFETs have been developed and applied to CMOS technologies ranging from 2mum down to 35nm. The first method uses a simple, RC propagation-delay model for inverters called the C&barbelow;onstant R&barbelow;C I&barbelow;nput-S&barbelow;ignal-T&barbelow;ransition-I&barbelow;nherent or CRISTI model. Constant RC values obtained from the CRISTI model give good approximations to inverter waveforms and delays obtained from SPICE. The second method uses a widely accepted "CV/ I" metric for characterizing transistors. This method is used to confirm the constant RC values obtained from the CRISTI model, and then it is used to project constant RC values for deep sub-micron CMOS technologies.;The CRISTI model was extended to more complex, multi-transistor (>2) logic gates. The model has been implemented into IRSIM, a previously existing timing analysis simulator. The new simulator is called C-IRSIM. Using constant RC values for a 0.18mum technology, C-IRSIM's estimates of propagation delay are within 10--15% of AIM-Spice values for static and dynamic digital CMOS circuits. C-IRSIM also offers ≈60% improvement over IRSIM. For a 1056-transistor 6-bit multiplier circuit, C-IRSIM demonstrates a 400x reduction in total execution time over AIM-Spice.;Constant RC values are also used in RIPE, the Rensselaer Interconnect Performance Estimator. RIPE allows one to investigate the effect of interconnect materials and strategies on microprocessor performance. RIPE is used to demonstrate the importance of having good RC values for MOSFETs by critically evaluating the very aggressive scaling trends proposed for CMOS technologies in the 1999 International Technology Roadmap for Semiconductors. Constant RC values are also used in the latest version of RIPE, RIPE 4.2, to perform an inductance optimization of on-chip wiring levels. This generally leads to a reduction of total wiring levels.;Finally, the methods of obtaining constant RC values are also applied to cryogenic (77K) CMOS and SOI CMOS.
机译:与标准电路仿真器(例如SPICE)(使用详细的非线性MOSFET模型)相比,在电路和时序分析工具中对MOSFET使用恒定电阻(R)和电容(C)模型可以显着减少总执行时间。已经开发出两种确定合适的MOSFET恒定RC值的方法,并将其应用于从2μm到35nm的CMOS技术。第一种方法是针对逆变器使用简单的RC传播延迟模型,称为C&barstant; Rstant& C I&barbelow; ignal-T&barbelow; ignal-T&barbelow; ransition-I&barbelow;固有或CRISTI模型。从CRISTI模型获得的恒定RC值可以很好地近似逆变器波形和从SPICE获得的延迟。第二种方法使用公认的“ CV / I”度量来表征晶体管。该方法用于确认从CRISTI模型获得的恒定RC值,然后用于投影深亚微米CMOS技术的恒定RC值。; CRISTI模型扩展到更复杂的多晶体管(> 2 )逻辑门。该模型已在IRSIM(以前存在的时序分析模拟器)中实现。新的模拟器称为C-IRSIM。对于0.18mum技术,使用恒定的RC值,对于静态和动态数字CMOS电路,C-IRSIM的传播延迟估计在AIM-Spice值的10--15%之内。与IRSIM相比,C-IRSIM还提供了≈ 60%的改进。对于1056晶体管的6位乘法器电路,C-IRSIM的总执行时间比AIM-Spice缩短了400倍。恒定的RC值也用于RIPE(Rensselaer互连性能估计器)。 RIPE允许人们研究互连材料和策略对微处理器性能的影响。 RIPE通过严格评估1999年《国际半导体技术路线图》中针对CMOS技术提出的非常激进的缩放趋势来证明MOSFET具有良好RC值的重要性。 RIPE的最新版本RIPE 4.2中还使用了恒定的RC值,以对片上布线电平进行电感优化。这通常会导致总布线量的减少。最后,获得恒定RC值的方法也应用于低温(77K)CMOS和SOI CMOS。

著录项

  • 作者

    Mark, Christopher Lawrence.;

  • 作者单位

    Rensselaer Polytechnic Institute.;

  • 授予单位 Rensselaer Polytechnic Institute.;
  • 学科 Electrical engineering.
  • 学位 Ph.D.
  • 年度 2000
  • 页码 335 p.
  • 总页数 335
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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