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An Electrical-Stimulus-Only BIST IC For Capacitive MEMS Accelerometer Sensitivity Characterization

机译:用于电容MEMS加速度计灵敏度表征的仅电刺激BIST IC

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摘要

Testing and calibration constitute a significant part of the overall manufacturing cost of microelectromechanical system (MEMS) devices. Developing a low-cost testing and calibration scheme applicable at the user side that ensures the continuous reliability and accuracy is a crucial need. The main purpose of testing is to eliminate defective devices and to verify the qualifications of a product is met. The calibration process for capacitive MEMS devices, for the most part, entails the determination of the mechanical sensitivity. In this work, a physical-stimulus-free built-in-self-test (BIST) integrated circuit (IC) design characterizing the sensitivity of capacitive MEMS accelerometers is presented. The BIST circuity can extract the amplitude and phase response of the acceleration sensor's mechanics under electrical excitation within 0.55% of error with respect to its mechanical sensitivity under the physical stimulus. Sensitivity characterization is performed using a low computation complexity multivariate linear regression model. The BIST circuitry maximizes the use of existing analog and mixed-signal readout signal chain and the host processor core, without the need for computationally expensive Fast Fourier Transform (FFT)-based approaches. The BIST IC is designed and fabricated using the 0.18-microm CMOS technology. The sensor analog front-end and BIST circuitry are integrated with a three-axis, low-g capacitive MEMS accelerometer in a single hermetically sealed package. The BIST circuitry occupies 0.3 mm 2 with a total readout IC area of 1.0 mm2 and consumes 8.9 mW during self-test operation.
机译:测试和校准构成了微机电系统(MEMS)装置总体制造成本的重要组成部分。迫切需要开发一种适用于用户端的低成本测试和校准方案,以确保连续的可靠性和准确性。测试的主要目的是消除有缺陷的设备并验证产品是否合格。电容性MEMS器件的校准过程大部分需要确定机械灵敏度。在这项工作中,提出了一种无物理刺激的内置自测(BIST)集成电路(IC)设计,该设计表征了电容MEMS加速度计的灵敏度。相对于物理刺激下的机械灵敏度,BIST电路可以在误差不超过0.55%的电激励下提取加速度传感器力学的幅度和相位响应。使用低计算复杂度的多元线性回归模型进行灵敏度表征。 BIST电路可最大限度地利用现有的模拟和混合信号读出信号链以及主机处理器内核,而无需使用基于计算的昂贵的基于快速傅立叶变换(FFT)的方法。 BIST IC是使用0.18微米CMOS技术设计和制造的。传感器模拟前端和BIST电路与三轴,低g电容式MEMS加速度计集成在一个密封的封装中。 BIST电路占用0.3 mm 2的空间,总读取IC面积为1.0 mm2,在自检操作期间消耗8.9 mW的功率。

著录项

  • 作者

    Ozel, Muhlis Kenan.;

  • 作者单位

    Arizona State University.;

  • 授予单位 Arizona State University.;
  • 学科 Electrical engineering.
  • 学位 Ph.D.
  • 年度 2017
  • 页码 82 p.
  • 总页数 82
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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