Low-power techniques for high-speed wireless baseband applications.

摘要

The application of digital techniques to every facet of electronic design continues to be a goal in the engineering community due to the many benefits of digitization (noise tolerance, precision control, increased functionality, programmability, etc.). As this goal is applied to the newest electronic markets, the highest-performance analog-to-digital (A/D) converters are required which tend to consume a large amount of power. In the growing area of wireless communications, large power consumption is contrary to battery life, motivating the search for low-power alternatives.; One possible low-power alternative is to perform some of the initial signal processing in the analog domain thereby relaxing the speed and/or resolution requirements of the A/D converter, thus lowering its power consumption. If the analog processing circuits dissipate roughly the same amount of power as the digital circuits they displaced, then the overall system power will be lower. The potential benefits of this analog approach is the motivation of this research.; The ideas and techniques developed in this work are applied to a integrated circuit (IC) prototype that implements a baseband data recovery system for a wireless direct-sequence, code-division multiple access (DS-CDMA) system. In the course of this research, the following contributions are presented: (1) a first-order relationship between power of an A/D converter and its speed (sampling rate) and resolution is derived, (2) a passive charge-error-cancellation technique is developed, permitting switched-capacitor integration without an operational amplifier, (3) low-power digital techniques are developed that further lower the dynamic power, (4) a CMOS DS-CDMA IC prototype capable of operation at 128MHz and dissipating 75mW is demonstrated.