This thesis discusses device physics, modeling and design issues of nanoscale transistors at the quantum level. The principle topics addressed in this report are (1) an implementation of appropriate physics and methodology in device modeling, (2) development of a new TOAD (technology computer aided design) tool for quantum level device simulation, (3) examination and assessment of new features of carrier transport in nanoscale transistors, and (4) exploration of device design issues near the ultimate scaling limit with the help of the developed tools. We concentrate on the technical issues by investigating a double-gate structure, which has been widely accepted as the ideal device structure for ultimate CMOS scaling. We focus on quantum effects and non-equilibrium, near-ballistic transport in extremely scaled transistors (in contrast to quasi-equilibrium, scattering-dominant transport in long channel devices), where a non-equilibrium Green's function formalism (NEGF) has been used to deal with the quantum transport problem.
展开▼
