Architecture design and mapping of DSP systems.

摘要

This thesis studies design methodologies for low power/high performance DSP VLSI systems with emphasis on architecture design and mapping. With system-on-chip (SOC) integration, more advanced DSP components and mixed signal processing systems are integrated on a single chip. As a result, design challenges associated with mapping advanced DSP components, meeting power consumption constraints, maintaining signal quality, etc., become severe. In this thesis, the design principles for handling these challenges with respect to certain DSP components are studied and proposed. These principles are also of great significance to other types of DSP components and can be used as general guidance in practical designs.; The first is using hierarchical approach and retiming technique to overcome design complexity. As an example, a design method for annihilation-reordering look-ahead QRD-RLS adaptive filters is proposed, where a uniform representation is derived. With this novel method, complicated pipelining and mapping of these filters can be designed in simple procedures.; The second is using computation reduction to achieve low power and low area. In this proposed example, by approximating the adaptive filtering, the Givens rotation based QRD-RLS adaptive filters can be implemented with much less power consumption and area occupation. Moreover, there is almost no change in the convergence rate of these approximate filters.; The third is exploring parallelism to obtain low latency and low power consumption simultaneously. To demonstrate this, the design of finite field multiplier is proposed, where latency is reduced with the parallelism and power consumption is also reduced due to switching activity reduction.; The last is using signal statistics to estimate power grid noise as well as power consumption at architecture level. For this purpose, the previous dual bit type (DBT) model for estimating power consumption is supplemented and new simple models for estimating power grid noise are developed. With improved DBT model, the power consumption can be more accurately estimated at architecture level. With the estimation of power grid noise by using the newly developed models, it is possible to achieve a better chip floor planning and power grid decoupling design, which is very important in mixed signal chips.