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A study on the reliability of flip chip solder joints.

机译:倒装芯片焊点可靠性的研究。

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Flip chip technology, as one of the most promising choices for high-density microelectronic connections, is the object of enormous amount of studies. Along with the appearance of new applications of this technology, such as chip-on-organic board technology and Pb-free solders, new reliability issues need to be addressed.; One of the most important issues is the on-chip metallizations. Low melting temperature solders such as eutectic Sn-Pb solder are needed for the low processing temperature when organic substrates are involved. The traditional Cu-containing metallizations, however, usually have a high dissolution rate in high-Sn solders and a high intermetallic compound formation rate with the reactive component Sn in the solders. These processes result in a high consumption rate of the metallization mainly during the soldering process but also in service. Consumption of all wetting metallization results in failure during either fabrication or service. The design of new metallizations for these situations will be discussed.; Fatigue of solder joints caused by thermally induced stresses is another important reliability issue. A finite element tool is utilized to study the thermal fatigue of the solder joints in a chip scale ball-grid-array (BGA) package. Viscoplasticity of the solder material is described in the finite element model with a constitutive law that is capable of capturing the rate-dependent plasticity of such materials. Fatigue lifetime of solder joints is predicted based on a plastic work approach.; Iso-thermal fatigue of solder joints of different sizes is studied experimentally based on a damage integral approach. A lifetime prediction model previously constructed is modified to take account of the reduction of the solder joint size. The effect of the size of the solder joints on the fatigue crack propagation rates is discussed.; Thermally induced stresses are not only an important reliability concern for solder joints, but also for on-chip interconnect lines. A finite element study is performed for confined Cu interconnect lines. Stiffness matrix of Cu is integrated in the finite element model to simulate the grain structure, and the thermal stress on the grain boundary between mis-oriented grains is studied and compared with experimental findings.
机译:倒装芯片技术作为高密度微电子连接的最有希望的选择之一,是大量研究的目标。随着这种技术的新应用的出现,例如有机板上芯片技术和无铅焊料,还需要解决新的可靠性问题。最重要的问题之一是片上金属化。当涉及有机基板时,为了达到低处理温度,需要使用低熔点温度的焊料(例如共晶Sn-Pb焊料)。然而,传统的含铜金属化通常在高锡焊料中具有高溶解速率,并且在焊料中具有反应性组分锡的金属间化合物形成速率高。这些过程主要在焊接过程中而且在使用中导致较高的金属消耗率。所有润湿金属化层的消耗都会导致制造或维修过程中的故障。将讨论针对这些情况的新金属化设计。由热应力引起的焊点疲劳是另一个重要的可靠性问题。利用有限元工具来研究芯片级球栅阵列(BGA)封装中焊点的热疲劳。焊料材料的粘塑性在本构关系的有限元模型中得以描述,该定律能够捕获此类材料的速率依赖性可塑性。焊点的疲劳寿命是根据塑性加工方法预测的。基于损伤积分法,对不同尺寸的焊点的等温疲劳进行了实验研究。修改先前构建的寿命预测模型以考虑减小焊点尺寸。讨论了焊点尺寸对疲劳裂纹扩展速率的影响。热应力不仅是焊点的重要可靠性问题,而且还是片上互连线的重要可靠性问题。对有限的Cu互连线进行了有限元研究。在有限元模型中集成了Cu的刚度矩阵,以模拟晶粒结构,研究了取向不正确的晶粒之间晶界上的热应力并将其与实验结果进行了比较。

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