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High performance CMOS amplifier and phase-locked loop design.

机译:高性能CMOS放大器和锁相环设计。

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摘要

Low voltage, high speed and high linearity are three different aspects of the analog circuit performance that designers are trying to achieve. In this dissertation, three design projects targeting these different performance optimizations are introduced.; The first work is a design of a low voltage operational amplifier. In this work, a threshold voltage tuning technique for low voltage CMOS analog circuit design is presented. A 750mV operational amplifier using this technique was designed in a 0.5μm 5V CMOS process with Vtp ≈ −0.9V and Vtn ≈ 0.8V. The active area is 560μm x 760μm. It exhibits a 62dB DC gain and consumes 38μW of power. It works with supply voltages from 0.75V to 1V. Compared to its 5V counterpart consuming the same amount of current, it maintains nearly the same gain bandwidth product of 3.7MHz. This op amp is the FIRST strong inversion op amp that works at a supply voltage below the threshold voltage.; The second is a design of a high speed phase-locked loop for data recovery. A new non-sequential linear phase detector is introduced in this work. Most of the existing phase detectors for data recovery are based on state-machines. The performance of these structures deteriorates rapidly at higher frequencies because of the inadequate settling performance of the flip-flop used to form the state machine. The new phase detector has a speed advantage over the state-machine based designs because it is simple and easy to implement in CMOS technology. Using this phase detector, a PLL was designed in a 0.25μm CMOS process with an active area of 400μm x 290μm. Experimental results show it successfully locks to a 2.1Gbit/s pseudo-random data sequence at 2.3V. It is believed that the architecture is the fastest that has been introduced for data recovery applications.; The third work introduces the design of a highly-linear variable gain amplifier. It achieves high linearity with third harmonic distortion better than −60dB@Vopp = 1V at 160MHz in a 0.25μm CMOS process. It has a precise gain step of 6.02dB that is controlled digitally. The linearity performance is achieved with a linearized open loop amplifier configuration. Similar performance could only be achieved using feedback configuration before.
机译:低压,高速和高线性度是设计人员试图实现的模拟电路性能的三个不同方面。本文介绍了针对这些不同性能优化的三个设计项目。首要工作是低压运算放大器的设计。在这项工作中,提出了一种用于低压CMOS模拟电路设计的阈值电压调整技术。采用 Vtp ≈的0.5μm5V CMOS工艺设计了使用该技术的750mV运算放大器。 −0.9V和 Vtn ≈ 0.8V。有效面积为560μmx760μm。它具有62dB的直流增益,并消耗38μW的功率。它可以在0.75V至1V的电源电压下工作。与消耗相同电流的5V同类产品相比,它保持了几乎相同的3.7MHz增益带宽积。该运算放大器是第一款强反相运算放大器,其工作电压低于阈值电压。第二个是用于数据恢复的高速锁相环的设计。在这项工作中引入了一种新的非顺序线性相位检测器。现有的大多数用于数据恢复的鉴相器都是基于状态机的。这些结构的性能在较高的频率下会迅速劣化,这是因为用于形成状态机的触发器的建立性能不足。与基于状态机的设计相比,新的相位检测器具有速度优势,因为它在CMOS技术中简单易行。使用该鉴相器,以0.25μmCMOS工艺设计了一个PLL,其有效面积为400μmx290μm。实验结果表明,它成功锁定了2.3V时的2.1Gbit / s伪随机数据序列。可以相信,该体系结构是为数据恢复应用程序引入的最快的体系结构。第三项工作介绍了高度线性可变增益放大器的设计。在0.25μmCMOS工艺中,它在160MHz时具有三次谐波失真优于−60dB @ Vopp = 1V的情况下实现了高线性度。它具有6.02dB的精确增益步进,可通过数字控制。线性性能是通过线性化开环放大器配置实现的。以前只能使用反馈配置才能获得类似的性能。

著录项

  • 作者

    Tang, Yonghui.;

  • 作者单位

    Iowa State University.;

  • 授予单位 Iowa State University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2002
  • 页码 116 p.
  • 总页数 116
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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