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Nanocrystalline and amorphous silicon thin film transistors deposited by microwave plasma electron cyclotron resonance chemical vapor deposition: Material analysis, device fabrication and characterization.

机译:微波等离子体电子回旋共振化学气相沉积法沉积的纳米晶和非晶硅薄膜晶体管:材料分析,器件制造和表征。

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摘要

Bottom-gated thin film transistors, employing ECR-CVD deposited nc-Si films as active channel layers, were fabricated, characterized and studied. These TFT's were fabricated at a low temperature range, 150°C–400°C and on different substrates, such as c-Si, quartz, glass and plastic. The effects of substrate temperatures and H2 dilutions during the Si film deposition on the film quality and TFT performance were studied. It was found that the TFT performance was improved as the substrate temperature and the H2 amount increased, including a higher mobility, a lower threshold voltage and a smaller subthreshold swing. This was due to the interaction of the H atom and nc-Si/a-Si network and the formation of strong Si-H and Si-Si bonds, which produced stable and high-performance TFT's.; Device-quality oxide was deposited at 150°C–300°C by PECVD using the decomposition of TEOS as the TFT gate dielectrics, which showed a high breakdown field of >8 MV/cm. The MOS capacitor C-V curves showed little stretch-out in the transition region and small horizontal shift compared with the theoretical C-V curve, which implied a low surface state density (∼10 11cm−2eV−1) at the Si/SiO 2 interface and a low density of fixed charges in the oxide.; The TFT performance is closely related to the active Si deposition conditions. For the TFT's with Si film deposited at 400°C with 10 mTorr H2, a mobility of 16.1 cm2/V-s, a threshold voltage of 2.6 V and a subthreshold swing of 0.45 V/decade were obtained for the TFT on a quartz substrate and a mobility of 13.3 cm2/V-s, a threshold voltage of 3.0V and a subthreshold swing of 0.48 V/decade were obtained for the TFT on a glass substrate. These TFT's had W/L of 200 μm/25 μm, which gave the best result among the several gate dimension designs. The incorporation of H2 during the deposition enhanced the crystallinity of the Si film, which was verified by the TEM measurements. For TFT's, the H2 incorporation not only passivated the dangling bonds in the active Si film but also filled the traps in the gate oxide near the Si/SiO2 interface, resulting in much-improved TFT characteristics, such as high on-current and steep subthreshold behavior. No post-hydrogenation process was carried out for these TFT's. The TFT's on plastic substrates were fabricated with a maximum temperature of 200°C, showing a mobility of 4.5 cm 2/V-s, a threshold voltage of 3.7 V and a subthreshold swing of 0.69 V/decade. The TFT's on plastic foil make the flexible, rugged and low-cost LCD applications possible. (Abstract shortened by UMI.)
机译:制备,表征和研究了采用ECR-CVD沉积的nc-Si膜作为有源沟道层的底栅型薄膜晶体管。这些TFT是在150°C至400°C的低温范围内并在不同的基板(例如c-Si,石英,玻璃和塑料)上制造的。研究了硅膜沉积过程中衬底温度和H 2 稀释对膜质量和TFT性能的影响。发现随着基板温度和H 2 含量的增加,TFT性能得到改善,包括更高的迁移率,更低的阈值电压和更小的亚阈值摆幅。这是由于H原子与nc-Si / a-Si网络的相互作用以及牢固的Si-H和Si-Si键的形成,从而产生了稳定而高性能的TFT。使用TEOS的分解作为TFT栅极电介质,通过PECVD在150°C–300°C的温度下沉积了器件质量的氧化物,其击穿场高> 8 MV / cm。与理论CV曲线相比,MOS电容器的CV曲线在过渡区域几乎没有延伸,水平位移也很小,这意味着表面态密度较低(〜10 11 cm -2 < / super> eV -1 )在Si / SiO 2 界面处,并且氧化物中固定电荷的密度低。 TFT性能与有源Si沉积条件密切相关。对于具有10 mTorr H 2 的400°C沉积的Si膜的TFT,迁移率为16.1 cm 2 / Vs,阈值电压为2.6 V,亚阈值摆幅石英基板上的TFT的导通电压为0.45 V / decade,而迁移率为13.3 cm 2 / Vs,阈值电压为3.0V,亚阈值摆幅为0.48 V / decade。在玻璃基板上的TFT。这些TFT的W / L为200μm/ 25μm,在几种栅极尺寸设计中给出了最好的结果。沉积过程中掺入H 2 增强了Si膜的结晶度,这已通过TEM测量得到了证实。对于TFT,H 2 结合不仅钝化了活性Si膜中的悬空键,而且填充了Si / SiO 2 界面附近的栅氧化层中的陷阱。 TFT特性得到了大大改善,例如高导通电流和陡峭的亚阈值行为。这些TFT没有进行后加氢处理。塑料基板上的TFT的最高温度为200°C,迁移率为4.5 cm 2 / V-s,阈值电压为3.7 V,亚阈值摆幅为0.69 V /十倍。塑料箔上的TFT使得灵活,坚固和低成本的LCD应用成为可能。 (摘要由UMI缩短。)

著录项

  • 作者

    Teng, Lihong.;

  • 作者单位

    State University of New York at Buffalo.;

  • 授予单位 State University of New York at Buffalo.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2003
  • 页码 202 p.
  • 总页数 202
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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