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Exploring Performance-Correctness Explicitly-Decoupled Architectures.

机译:探索性能正确的显式解耦体系结构。

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摘要

Optimizing the common case has been an adage in decades of processor design practices. However, as the system complexity and optimization techniques' sophistication have increased substantially, maintaining correctness under all situations, however unlikely, is contributing to the necessity of extra conservatism in all layers of the system design. The mounting process, voltage, and temperature variation concerns further add to the conservatism in setting operating parameters. Excessive conservatism in turn hurts performance and efficiency in the common case. However, much of the system's complexity comes from advanced performance features and may not compromise the whole system's functionality and correctness even if some components are imperfect and introduce occasional errors. In this thesis, we propose to separate performance goals from the correctness goal using an explicitly-decoupled architecture.;As a proof-of-concept, we discuss two such incarnations for an out-of-order microprocessor. First, we discuss how explicitly-decoupled architecture can be used to implement an efficient mechanism to track and enforce memory dependences. Later, we discuss enhancements to improve traditional ILP (instruction-level parallelism). In both the designs a decoupled performance enhancement engine performs optimistic execution and helps an independent correctness engine by passing high-quality predictions. The lack of concern for correctness in the performance domain allows us to optimize its execution in a more effective fashion than possible in optimizing a monolithic design with correctness requirements. In this thesis we show that such a decoupled design allows significant optimization benefits and is much less sensitive to conservatism applied in the correctness domain.
机译:在数十年的处理器设计实践中,优化常见情况一直是一句谚语。但是,由于系统复杂性和优化技术的复杂性已大大提高,因此在所有情况下保持正确性(无论多么不可能)都导致在系统设计的所有层级都需要额外的保守性。安装过程,电压和温度变化问题进一步增加了在设置操作参数方面的保守性。在通常情况下,过度的保守主义反过来会损害性能和效率。但是,系统的大部分复杂性来自高级性能功能,即使某些组件不完善并且偶尔会出现错误,也可能不会损害整个系统的功能和正确性。在本文中,我们建议使用显式解耦的体系结构将性能目标与正确性目标分离。作为概念验证,我们讨论了无序微处理器的两种化身。首先,我们讨论如何使用显式解耦的体系结构来实现一种有效的机制来跟踪和强制执行内存依赖性。稍后,我们将讨论增强功能以​​改进传统的ILP(指令级并行性)。在这两种设计中,解耦的性能增强引擎均执行乐观执行,并通过传递高质量的预测来帮助独立的正确性引擎。与性能方面的正确性无关,这使我们能够以比对具有正确性要求的整体设计进行优化的方式更有效的方式优化其执行。在本文中,我们证明了这种解耦设计具有显着的优化优势,并且对正确性领域中应用的保守性不那么敏感。

著录项

  • 作者

    Garg, Alok.;

  • 作者单位

    University of Rochester.;

  • 授予单位 University of Rochester.;
  • 学科 Engineering Computer.
  • 学位 Ph.D.
  • 年度 2011
  • 页码 157 p.
  • 总页数 157
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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