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Low-power double-sampled delta-sigma modulator for broadband applications.

机译:用于宽带应用的低功耗双采样delta-sigma调制器。

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摘要

High speed and high resolution analog-to-digital converter (ADC) is a key building block for broadband wireless communications, high definition video applications, medical images and so on. By leveraging the down scaling of the latest CMOS technology and the noise shaping properties, delta-sigma (DeltaSigma) ADCs are able to achieve wide-band operation and high accuracy simultaneously. In this thesis, two novel techniques, which can be applied to high performance DeltaSigma ADC design, are proposed. The first one is a modulator architectural innovation that is able to effectively solve the feedback timing constraints in a double-sampled DeltaSigma modulator. The second one is a transistor level improvement to reduce the hardware consumption in a standard Data Weighted Averaging (DWA) realization.;Next, charge-pump (CP) based switched-capacitor (SC) integrator is discussed. A cross-coupling technique is proposed to eliminate parasitic capacitor effect in a CP based SC integrator. Also, design methodologies are introduced to incorporate a modified CP based SC integrator into a low-distortion DeltaSigma modulator. A second-order DeltaSigma modulator was designed and simulated to verify the proposed modulator topology.;Finally, the design of a double-sampled broadband 12-bit DeltaSigma modulator is presented. To achieve very low power consumption, this modulator utilizes the following two key design techniques: (1) Double sampled integrator to increase the effective over-sampling ratio. (2) Capacitor reset technique allows the use of only one feedback DAC at the front end of the modulator to completely eliminate the quantization noise folding back.;A 2+2 cascaded topology with 3-bit internal quantizer is used in this DeltaSigma modulator to adequately suppress the quantization noise while guaranteeing the loop stability. This DeltaSigma modulator was fabricated in a 90 nm digital CMOS process and achieves an SNDR of 70 dB within a 5 MHz signal bandwidth. The modulator occupies a silicon area of 0.5 mm2 and consumes 10 mW with a supply voltage of 1.2 V.
机译:高速,高分辨率模数转换器(ADC)是宽带无线通信,高清视频应用,医学图像等的关键组成部分。通过利用最新CMOS技术的缩小比例和噪声整形特性,Δ-Σ(DeltaSigma)ADC能够同时实现宽带工作和高精度。本文提出了两种可以应用于高性能DeltaSigma ADC设计的新技术。第一个是调制器架构创新,它能够有效解决双采样DeltaSigma调制器中的反馈时序约束。第二个是晶体管级的改进,以减少标准数据加权平均(DWA)实现中的硬件消耗。接下来,讨论基于电荷泵(CP)的开关电容器(SC)积分器。提出了一种交叉耦合技术,以消除基于CP的SC积分器中的寄生电容器效应。此外,还引入了设计方法,以将改进的基于CP的SC积分器整合到低失真DeltaSigma调制器中。设计并仿真了二阶DeltaSigma调制器,以验证所提出的调制器拓扑。最后,提出了双采样宽带12位DeltaSigma调制器的设计。为了实现极低的功耗,该调制器利用以下两项关键设计技术:(1)双采样积分器可提高有效过采样率。 (2)电容复位技术仅允许在调制器的前端使用一个反馈DAC来完全消除量化噪声折返。该DeltaSigma调制器使用具有3位内部量化器的2 + 2级联拓扑来在保证环路稳定性的同时充分抑制量化噪声。该DeltaSigma调制器采用90 nm数字CMOS工艺制造,在5 MHz的信号带宽内达到了70 dB的SNDR。调制器占用0.5 mm2的硅面积,在1.2 V的电源电压下消耗10 mW的功率。

著录项

  • 作者

    Shen, Weilun.;

  • 作者单位

    Oregon State University.;

  • 授予单位 Oregon State University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2011
  • 页码 119 p.
  • 总页数 119
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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