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A wideband, time-interleaved CMOS A/D converter using photoconductive sampling switches.

机译:使用光电导采样开关的宽带,时间交错的CMOS A / D转换器。

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摘要

High-speed analog-to-digital (A/D) conversion of signals with bandwidths of several tens of gigahertz would enable a number of digital signal processing applications in fiber-optic communications, wideband radar and high-speed instrumentation. However, current electronic A/D converter technology is at best capable of 4 to 8 effective bits of resolution for signal bandwidths as high as a few GHz. A number of optical sampling techniques have been proposed to provide much higher input bandwidths while taking advantage of low-jitter mode-locked laser sources to improve resolution. However, most of these techniques have been difficult to integrate with conventional electronic A/D converters.; This work introduces a parallel A/D conversion architecture wherein a large number of time-interleaved channels each combine photonic sampling with a 4-bit, 800-MSample/s CMOS A/D converter. Each channel samples the electrical input signal using ultrafast photoconductive switches that are fabricated in low-temperature-grown (LT-grown) GaAs and flip-chip bonded onto a CMOS integrated circuit chip. When optically-triggered with a short-pulse laser, the photoconductive switches provide sampling apertures of a few picoseconds with about 6 bits of linearity, but they have limited drive capability.; The design of the 4-bit CMOS A/D converters used to digitize the sampled signals is constrained by the need for a very low input capacitance and a small area, the latter necessary to allow the integration of many converters in a single chip to maximize the aggregate sampling rate. The A/D converters each consist of a linearized open-loop buffer amplifier followed by a 4-bit flash quantizer. Dynamic averaging of offsets in the flash quantizer relaxes transistor matching requirements, thus reducing the circuit area. The use of optically-triggered sampling and time-interleaving relaxes the jitter, timing skew and conversion rate requirements of the CMOS A/D converters.; Measurement results are presented for an experimental 2-channel, 4-bit photoconductive-sampling A/D converter fabricated in a 0.25-mum CMOS technology with flip-chip bonded LT-grown GaAs switches. The prototype provides about 3.5 effective bits of resolution for input frequencies up to 40 GHz, with an estimated sampling jitter of less than 80 fs. Each channel dissipates 70 mW of power at a 640-MHz conversion rate and occupies an active area of 150 mum by 450 mum.
机译:带宽为数十GHz的信号的高速模数(A / D)转换将使光纤通信,宽带雷达和高速仪器中的许多数字信号处理应用成为可能。但是,对于高达几GHz的信号带宽,当前的电子A / D转换器技术最多只能具有4到8个有效位的分辨率。已经提出了许多光学采样技术来提供更高的输入带宽,同时利用低抖动锁模激光源来提高分辨率。但是,大多数这些技术很难与常规电子A / D转换器集成。这项工作引入了并行A / D转换架构,其中大量的时间交错通道将光子采样与4位800-MSample / s CMOS A / D转换器相结合。每个通道都使用超快速光电导开关对电输入信号进行采样,该开关以低温生长(LT生长)GaAs制成,并倒装芯片结合到CMOS集成电路芯片上。当用短脉冲激光光学触发时,光电导开关提供了几皮秒的采样孔径和大约6位的线性度,但是它们的驱动能力有限。用于数字化采样信号的4位CMOS A / D转换器的设计受到对非常低的输入电容和小面积的需求的限制,后者对于允许将多个转换器集成在单个芯片中以使其最大化是必需的总采样率。每个A / D转换器均由一个线性化的开环缓冲放大器和一个4位闪存量化器组成。闪速量化器中偏移的动态平均可减轻晶体管匹配要求,从而减小电路面积。光学触发采样和时间交织的使用减轻了CMOS A / D转换器的抖动,时序偏斜和转换速率要求。给出了采用0.25微米CMOS技术制造的带有倒装键合LT生长的GaAs开关的2通道,4位光电导采样A / D转换器的实验结果。该原型为高达40 GHz的输入频率提供约3.5有效分辨率分辨率,估计的采样抖动小于80 fs。每个通道以640 MHz的转换速率耗散70 mW的功率,并占用150 m x 450 mm的有效面积。

著录项

  • 作者

    Nathawad, Lalitkumar Y.;

  • 作者单位

    Stanford University.;

  • 授予单位 Stanford University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2004
  • 页码 158 p.
  • 总页数 158
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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