A hardware/software co-design approach for face recognition by artificial neural networks.

摘要

Artificial Neural Networks (ANNs), and the multi-layer perceptrons trained using an error backpropagation algorithm (MLP-BP) in particular, have proven to be an effective method today in many applications. However, this technique has suffered from slow training and lack of clear methodology to determine the network topology before training starts. The speedup to this algorithm is desired so that reasonable experimentation with various network topologies and on-line working are possible. Although Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) can achieve speedup over a general processor, the flexibility is a tradeoff with speed. To balance them, an embedded computing system consisting both a processor with dedicated hardware on an FPGA chip is proposed. Results obtained show that this system achieves 1.69 speedup (Amdahl's Law) over the system which consists of only a processor on an FPGA chip. At the same time, the flexibility is preserved to some extent.