Commercially available Field Programmable Gate Arrays (FPGAs) have reached a high level of adoption and replaced more expensive alternatives in several fields. They are today used as computational devices, as test devices and as replacements to Application Specific Integrated Circuits (ASICs). Today's FPGAs can be electrically programmed but do not retain information once powered down. Non-volatility would lead to significantly more power effective implementation of designs; operation could be suspended and virtually instantaneously resumed leading to power savings.;Recent developments in Magnetic Tunnel Junction (MTJ) technology allow the use of these components as non-volatile memory elements in CMOS based designs. However, behavioral models for these devices have never been simulated at the transistor level in large scale architectures. Therefore, a traditional block-based volatile FPGA architecture is introduced. In order to transition to an MTJ/CMOS-hybrid FPGA, it is concluded that some elements remain unchanged whereas others need substantial change to include MTJs. This leads to the integration of upgraded and untouched blocks into an FPGA of minimum size. A sample circuit is programmed on the latter and successfully simulated. This leads to conclusions establishing the possibility of simulating architectures involving MTJs and, the possibility of creating a sound MTJ-based FPGA. Designs are proposed and tested in Cadence Virtuoso and Spectre.
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