Silicon recording arrays with integrated circuitry for in-vivo neural data compression.

摘要

This thesis presents the design, testing, implantation and limitations of neural recording arrays with integrated CMOS circuitry. A fully-implantable 3D neural recording microsystem has been developed that features site selection, amplification, time-division multiplexing, and spike detection circuitry. The fundamental limits and tradeoffs involving size, power consumption, multiplexer speed, quantization noise, spike detection and discrimination, and neural data compression have been analyzed and presented. The 256-site 3D microsystem is capable of recording up to 32 channels of simultaneous neural signals at a data rate that is compatible with current transcutaneous telemetry platforms.; A capacitively-coupled neural recording amplifier has been developed to solve the do baseline stabilization problem. The amplifier uses subthreshold NMOS transistors with an incremental resistance of greater than 10 10 O to realize an integrated high-pass filter below 100Hz while providing an in-band gain of 39dB. The amplifier has a high-frequency cutoff of 9.9kHz for anti-aliasing, and the low-frequency cutoff of the amplifier is tunable. The total integrated noise of the amplifier from 100Hz to 10kHz is 9.2muVrms, which is lower than that of a 165mm2 iridium electrode in saline. The amplifier consumes 84muW of power from +/-1.5V supplies and occupies 0.177mm2 in 3mum features. The performance of this amplifier has been evaluated during hundreds of hours of in-vivo experiments.; This thesis presents amplified, time-division-multiplexed neural recordings for the first time. The design and limitations of time-division multiplexers are presented including the tradeoffs among supply scaling, load capacitance, sampling frequency, and number of channels. The current multiplexer design samples 8 neural channels onto a single output lead at a sampling frequency of 20kHz/channel.; A spike detection ASIC has been developed to compress the neural data in-vivo, allowing hundreds of channels to be recorded simultaneously over a wireless interface. The spike detector successfully detects neural spikes in the presence of neural and circuit noise and achieves a bandwidth savings of 92% while still preserving the key features of the waveshape necessary for spike discrimination. When a spike is detected, this ASIC serially shifts the 5-bit amplitude and 5-bit address of the spike off of the chip over a single data lead at 2.5Mbps. The spike detection ASIC occupies 2mm x 3mm in 0.5mum features and consumes 2.6mW of power from a 3V supply. Tradeoffs in terms of power consumption and circuit area to improve the performance of the spike detection ASIC are presented.