首页> 外国专利> Arrays comprising vertically-oriented transistors, integrated circuitry comprising a conductive line buried in silicon-comprising semiconductor material, methods of forming a plurality of conductive lines buried in silicon-comprising semiconductor material, and methods of forming an array comprising vertically-oriented transistors

Arrays comprising vertically-oriented transistors, integrated circuitry comprising a conductive line buried in silicon-comprising semiconductor material, methods of forming a plurality of conductive lines buried in silicon-comprising semiconductor material, and methods of forming an array comprising vertically-oriented transistors

机译:包括垂直取向的晶体管的阵列,包括埋在含硅半导体材料中的导线的集成电路,形成埋在包含硅的半导体材料中的多条导线的方法以及形成包括垂直取向的晶体管的阵列的方法

摘要

An array includes vertically-oriented transistors, rows of access lines, and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The data/sense line has silicon-comprising semiconductor material between the transistors in that column that is conductively-doped n-type with at least one of As and Sb. The conductively-doped semiconductor material of the data/sense line includes a conductivity-neutral dopant between the transistors in that column. Methods are disclosed.
机译:阵列包括垂直取向的晶体管,访问线的行和数据/检测线的列。这些行中的各个行包括将该行中的晶体管互连的访问线。各个列包括在该列中互连晶体管的数据/检测线。数据/传感线在该列中的晶体管之间具有含硅的半导体材料,该半导体材料被导电地掺杂有As和Sb中的至少一种的n型。数据/传感线的导电掺杂半导体材料在该列中的晶体管之间包括中性导电掺杂剂。公开了方法。

著录项

  • 公开/公告号US9129896B2

    专利类型

  • 公开/公告日2015-09-08

    原文格式PDF

  • 申请/专利权人 YONGJUN JEFF HU;ALLEN MCTEER;

    申请/专利号US201213591065

  • 发明设计人 YONGJUN JEFF HU;ALLEN MCTEER;

    申请日2012-08-21

  • 分类号H01L29/66;H01L21/265;H01L29/78;H01L27/108;

  • 国家 US

  • 入库时间 2022-08-21 15:18:14

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