Reconfigurable cellular arrays for molecular electronics.

摘要

Reconfigurable circuit architecture and interconnection distribution concepts suitable for implementation at a molecular scale were developed, analyzed, and compared to conventional field programmable gate arrays (FPGAs). The concepts, referred to as reconfigurable cellular arrays (RCAs), are periodic template structures based on time-unrolled cellular automata, where each site is replaced by a circuit lookup table (LUT). Universality of these templates to implement any Boolean circuit has been shown, and details of a prospective molecular/VLSI implementation developed. This implementation includes an interconnect distribution system based on three-dimensional nanowires in a random distribution that yields statistical behavior similar to complex VLSI interconnect manifolds, number of methods for Boolean synthesis integrated heuristics (based on modified heuristics, including greedy placement, string-edit distance, and pseudo-programmable logic array (PLA) heuristics. A were examined, including artificial neural networks) and The latter approach involved a set of methods, and tree matching, The latter method, exploiting a connection between RCA and programmable logic array (PLA) structures, was implemented as a layout program. Using this program, a number of standard benchmarks and random circuits were analyzed and compared to comparable results for Xilinx and Altera FPGAs. The size of all FPGAs (normalized to square lambda) as a function of input circuit size is shown empirically to be nonlinear and worse for RCAs than traditional FPGAs. Furthermore, for RCAs, the growth is shown to be quadratic in circuit size as is the growth in crossing number, which impacts the ability to make compact implementations of very complex circuits. The factors that contribute to this are both tool-related and a property of the interconnections of circuits being targeted for implementation in RCAs or FPGAs. A method for "layout-friendly" synthesis, which amounts to a new method that integrates decomposition, placement, and routing was developed and demonstrated on simple circuits as a potential solution for minimizing the impact of tools on synthesis efficiency.