This dissertation presents new signaling schemes and circuit architectures for reducing the power and cost of high-speed chip-to-chip links. After an overview on chip-to-chip interconnects and its building blocks, a new signaling scheme is proposed that can provide many advantages of a fully-differential signaling scheme while employing as few as N + 1 signal paths for communicating N differential signals. Next, power-efficient signaling schemes that use channel coding to achieve appreciable coding gain are proposed. One discussed method is to use 6-PAM signaling instead of 4-PAM to transmit two bits of information per channel. The proposed low-complexity architecture of this scheme makes its high-speed implementation feasible. A realistic model for a typical interconnect channel is used for simulations. We then introduce a coding scheme which employs a convolutional encoder in space to achieve 3--5 dB coding gain without expanding the modulation from 4-PAM to 6-PAM. The functionality and performance of the proposed scheme is verified by experimental results obtained from a fabricated chip based on this method. Finally, a novel power-efficient architecture for multi-level PAM drivers is presented. In addition, a data-look-ahead technique, used for high-speed implementation of this method, eliminates the need for a pre-driver to further reduce the driver power. Based on this architecture, a 4-PAM transmitter is designed in 0.18mum digital CMOS technology. The transmitter achieves 10 Gb/s with a 2-V supply and it occupies an area of 0.16 mm2. The output driver and the entire transmitter consume only 20 mW and 121 mW at 10 Gb/s, respectively, which are the lowest reported powers at this speed.
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