Hierarchical design space exploration for efficient application design using heterogeneous embedded system.

摘要

Heterogeneous embedded systems integrate multiple programmable components such as microprocessors, micro-controllers, digital signal processors, and field programmable gate arrays and memory into a single system. During application design using heterogeneous embedded systems, the availability of multiple programmable components enable the exploration of a tradeoff among key performance metrics such as energy, latency, and area. Features, of the integrated devices, such as reconfiguration, voltage and frequency scaling, low power operating states, efficient start up and shut down, among others, are exploited by the designer to meet the given latency and energy constraints. However, a large number of choices during such exploration result in a large design space that must be explored efficiently. Traditional approaches of using low-level simulators are extremely time-consuming and thus fail to perform efficient exploration. In addition, due to lack of a common interface standard and varying simulation speeds, it is extremely difficult to integrate these simulators to simulate a heterogeneous embedded system. On the other hand, optimization heuristics based on high-level models are extremely fast. However, due to simplifying assumptions while defining high-level models, performance estimation and design space exploration based on such models are susceptible to error. In this dissertation, we propose a hierarchical methodology that integrates design space pruning heuristics, a high-level performance estimator, and low-level simulators to enable efficient exploration of large design spaces. Through such integration, our methodology exploits the speed versus accuracy tradeoffs to perform faster and more accurate evaluation of large design spaces. We applied the proposed methodology to the domain of low power high performance signal processing application design using heterogeneous embedded systems based on a given duty cycle specification. Our methodology was demonstrated to be approximately three orders of magnitude faster while producing similar results when compared with design space exploration using low-level simulators. In addition, we demonstrated robustness against approximation errors through identification of designs with lower latency or energy dissipation compared to the results obtained through heuristic based approaches. We have also developed a unified extensible design framework based on the model integrated computing approach.