Interaction of metal gates with high -k gate dielectrics in advanced CMOS devices.

摘要

The continued scaling of CMOS devices beyond the 45 nm node requires successful integration of dual work function metal gate electrodes with high-k gate dielectrics. Recent reports have shown the feasibility of hafnium based high-k gate dielectrics in advanced CMOS devices. However, achieving the appropriate band-edge effective work function (phim,eff) of metal gates compatible for NMOS and PMOS devices in self aligned process of CMOS fabrication has been a focus of tremendous research. Most of the candidate metal gates suffer from the instability in phim,eff after high temperature anneals leading to a high threshold voltage of devices. The cause of this instability is still unclear. While some of the current reports have proposed solutions for NMOS metal gates through metal/high-k interface engineering, the solution for PMOS metal gates still remains unsolved.;The purpose of this research is to understand the various factors that govern the phim,eff of metal gate electrodes on high-k gate dielectrics. A unified methodology to decouple the various factors contributing to the phi m,eff is developed and implemented to understand the experimental data. Using this methodology, the Fermi level pinning and thermal stability of various candidate metal gates on high-k gate dielectrics are evaluated. In order to understand the origin of instability in the phim,eff of PMOS metals, the dependence of phim,eff on intentionally modulated surfaces of high-k gate dielectrics is investigated intensively through systematic experiments. An in-depth characterization of the metal/high-k interface is carried out using X-Ray Photoelectron Spectroscopy (XPS), Ultraviolet Photoelectron Spectroscopy (UPS), High Resolution Transmission Electron Microscopy (HRTEM) and Electron Energy Loss Spectroscopy (EELS) to understand the origin of dipoles. The process integration issues associated with the PMOS metals such as the impact of an adhesion layer at metal/high-k interface and the role of a capping layer in the gate stack on modulating the phim,eff are also addressed. Based on these observations, routes to achieve PMOS compatible phi m,eff of metals on ultra thin EOT HfO2 gate dielectric under stringent thermal budget are proposed and supported with encouraging results. These findings are critical in understanding the metal gates/high-k interface and engineering a PMOS solution.