Time-interleaved ADC for high-speed communications.

摘要

Wireline communication has increasingly high demand on data rate. Channel loss is problematic for high speed transmission. Conventionally, analog equalizers are used to alleviate the problem. But recently, people have proposed an ADC/DSP based equalization scheme which directly digitizes the incoming attenuated data and then makes use of the flexibility of the DSP to conduct the equalization in the pure digital domain.;In this dissertation, we propose a new high-speed time-interleaved analog-to-digital converter (ADC) design that achieves power efficiency better than the state-of-the-art. A new ADC structure, namely partially-active (PA) flash ADC, is proposed for the implementation of the sub-ADC design. A new source-follower based bootstrap track-and-hold circuit is also developed to reduce the input kickback noise. Furthermore, we propose a simplified multi-phase clock generation scheme. The scheme is based on extracting an input master clock with a pass gate. Because the delay of the pass gate is very short, the resulting timing skews among the sub-ADC channels can be much reduced. The residual timing skew is calibrated out through simple duty cycle correction. To verify our proposed techniques, a 10-GS/s 6-bit time-interleaved ADC prototype was designed. The measurement results show that the test chip consumes 83mW and has achieved figure-of-merit of 197fJ/conv-step. At the low input frequency, the ADC has SNDR of 34.0dB and SFDR of 51.0dB. The corresponding ENOB is 5.4. At 5GHz Nyquist frequency, the ADC has SNDR of 32.0dB and SFDR of 44.7dB. The active die area of the ADC is 0.2 mm2. An open-loop 10GHz 8-phase clock generator is also presented in this dissertation. The open-loop architecture, with built-in compensation technique for the delay time variation, is composed of delay units and phase interpolators. The delay unit is designed with level-shifted active inductor load for power efficient delay operation achieving an efficiency of 0.19mW/GHz/phase at 10GHz. The active inductor is also made scalable to operate at different frequency. The 8-phase clock generator generates output clocks with good phase accuracy and occupies 1500μm2 die area.