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Low-noise, fast-response low-drop-out regulators for RF applications.

机译:适用于RF应用的低噪声,快速响应的低压降稳压器。

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摘要

As CMOS technology is rapidly moving to deep submicron gate lengths, supply voltages for analog and RF circuitry are continuously decreasing. This introduces new challenges for the design of RF and analog circuits. One of the main challenges is the drastic reduction on the supply voltage which limits the linearity, dynamic range, and increases the supply ripple sensitivity of the circuits. With the reduction of the RF IC's supply voltage, noise, ripple and cross-coupling on the power supply starts playing a dominant role in the transceiver noise budget. To overcome noise budget in analog and RF circuitry, well-designed voltage regulators are required. This regulator should have low noise and fast transient characteristics for improving analog and RF circuits' performance and also requires good current efficiency for battery life.; The proposed research consists of designing, modeling, and characterizing three types of low-dropout (LDO) regulator architectures. The focus is on low-power portable applications such as mobile phones, PDAs and laptops, where small area, low cost, low noise, high power supply rejection and high efficiency are the primary design objectives. The first proposed LDO regulator utilizes a current feedback buffer amplifier to achieve fast transient response. The other two LDO regulators focus on low noise characteristics for RF applications. The second proposed LDO regulator is a low 1/f noise LDO regulator which employs chopper stabilization techniques. Using a chopper stabilization technique, noise at low frequencies of the error amplifier, which is one of the dominant noise sources, especially 1/f noise, is surprisingly reduced. This technique is also used to reduce output noise of the reference circuit, which is another dominant noise source in LDO regulators. To improve power supply rejection (PSR), a supply rejection subtraction stage has been included. The third proposed LDO regulator utilizes chopper stabilization techniques to reduce 1/f noise at low frequencies, a current feedback amplifier to improve transient response, and a delta-sigma (DeltaSigma) noise shaper to reduce the tonal energy at the chopping frequency due to clock feedthrough via chopper switches. Three types of LDO regulators could be utilized as a power management circuitry in RF applications.
机译:随着CMOS技术迅速发展到深亚微米栅极长度,用于模拟和RF电路的电源电压正在不断降低。这给射频和模拟电路的设计提出了新的挑战。主要挑战之一是大幅降低电源电压,这限制了线性度,动态范围,并增加了电路的电源纹波灵敏度。随着RF IC电源电压的降低,电源上的噪声,纹波和交叉耦合开始在收发器噪声预算中起主导作用。为了克服模拟和RF电路中的噪声预算,需要精心设计的稳压器。该稳压器应具有低噪声和快速瞬态特性,以改善模拟和RF电路的性能,并且还要求良好的电流效率以延长电池寿命。拟议的研究包括设计,建模和表征三种类型的低压差(LDO)稳压器架构。重点是低功耗便携式应用,例如手机,PDA和便携式计算机,这些应用的主要设计目标是小面积,低成本,低噪声,高电源抑制比和高效率。最早提出的LDO稳压器利用电流反馈缓冲放大器来实现快速瞬态响应。另外两个LDO稳压器专注于RF应用的低噪声特性。提出的第二个LDO稳压器是采用斩波稳定技术的低1 / f噪声LDO稳压器。使用斩波器稳定技术,令人惊讶地减少了误差放大器的低频噪声,该噪声放大器是主要噪声源之一,尤其是1 / f噪声。此技术还用于降低基准电路的输出噪声,该电路是LDO稳压器中的另一个主要噪声源。为了改善电源抑制(PSR),已经包括了电源抑制减法阶段。提出的第三个LDO稳压器利用斩波器稳定技术来降低低频下的1 / f噪声,一个电流反馈放大器来改善瞬态响应,以及一个delta-sigma(DeltaSigma)噪声整形器来降低由于时钟引起的斩波频率下的音调能量。通过斩波开关的馈通。三种类型的LDO稳压器可用作RF应用中的电源管理电路。

著录项

  • 作者

    Oh, Wonseok.;

  • 作者单位

    Arizona State University.;

  • 授予单位 Arizona State University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2006
  • 页码 152 p.
  • 总页数 152
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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