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Reducing inductive effects in radio frequency integrated circuits.

机译:减少射频集成电路中的感应效应。

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摘要

The continuous scaling of silicon CMOS technology has improved the performance of CMOS integrated circuits (ICs) enough to enable operation at radio frequencies (RF). Consequently, increasingly large portions of RFICs are being made in CMOS technology due to widespread availability and relatively low cost. Examples include wireless networks, GPS, cellular phones, and Bluetooth.;With the advent of silicon RFICs, circuit designers have been taking advantage of inductance to build many different RF circuit blocks from voltage-controlled oscillators (VCOs) to tuned amplifiers. Consequently, on-chip inductors have become key components in RF circuits and can be clearly seen on many chip layouts. However, the higher frequencies and higher levels of integration that accompany scaling begin to exacerbate some unwanted inductive effects. In particular, inductors in close proximity exhibit magnetic crosstalk that results in more interference, and interconnect shows more loss at higher operating frequencies. These effects are significant in modern communication circuits where interference or loss in signal power directly hampers circuit operation.;This work investigates techniques to reduce these unwanted inductive effects in an IC environment. A new inductor structure, the quadrupole inductor, results in less crosstalk and is used in a VCO to demonstrate improved isolation from neighboring interferers. Also, a slotted ground shields are used in conjunction with coplanar waveguides (CPWs) to create low-loss interconnect. Results from this research show that the quadrupole inductor can reduce crosstalk by 30 dB and CPWs with slotted ground shields exhibit a low loss of -0.42 dB/mm at 45 GHz.
机译:硅CMOS技术的不断扩展已经充分提高了CMOS集成电路(IC)的性能,从而可以在射频(RF)下运行。因此,由于广泛的可用性和相对较低的成本,越来越多的RFIC用CMOS技术制成。示例包括无线网络,GPS,蜂窝电话和蓝牙。随着硅RFIC的出现,电路设计人员已开始利用电感来构建从压控振荡器(VCO)到调谐放大器的许多不同的RF电路模块。因此,片上电感器已成为RF电路中的关键组件,并且可以在许多芯片布局中清晰看到。但是,伴随缩放的更高频率和更高集成度开始加剧一些不必要的感应效应。特别是,紧邻的电感器会产生磁串扰,从而导致更多的干扰,而互连在较高的工作频率下会显示出更多的损耗。这些影响在现代通信电路中非常重要,在现代通信电路中,信号功率的干扰或损耗直接阻碍了电路的工作。一种新的电感器结构,即四极电感器,可减少串扰,并在VCO中使用,以证明与相邻干扰源的隔离度得到改善。此外,开槽接地屏蔽与共面波导(CPW)结合使用可创建低损耗互连。这项研究的结果表明,四极电感器可以减少30 dB的串扰,带有开槽接地屏蔽的CPW在45 GHz频率下的损耗仅为-0.42 dB / mm。

著录项

  • 作者

    Poon, Andrew.;

  • 作者单位

    Stanford University.;

  • 授予单位 Stanford University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2008
  • 页码 102 p.
  • 总页数 102
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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