ITERATIVE IMPROVEMENT HEURISTICS FOR THE STANDARD CELL PLACEMENT: A COMPARISON

摘要

As we move to deep sub-micron designs below 0.18 microns, the delay of a circuit, as well as power dissipation and area, is dominated by interconnections between logical elements (i.e. transistors). This paper introduces and compares several iterative heuristic search techniques for the Standard Cell VLSI Placement problem. Iterative improvement methods are important for the circuit layout due to their flexibility and capability of producing high quality placements in reasonable time. Results obtained indicate that the Tabu Search approach yields the best solution quality whereas the Tile search heuristic generates similar solutions in less than half the CPU time.