Standard cell placement method to exercise placement permutations of standard cell libraries

摘要

A method for validating standard cells stored in a standard cell library and for use in design of an integrated circuit device is described. Each standard cell of the standard cells is iteratively placed adjacent to each side and corner of itself and each other standard cell of the standard cells to produce an interim test layout comprising a first plurality of cell pair permutations. The cell pair permutations are reduced by identifying at least one of: illegal or redundant left-right and top-bottom boundaries, and removing any cell pair permutations using the identified boundaries to generate a final test layout comprising a second plurality of cell pair permutations.