Design Considerations for Real-Time System-On-Chip Applications

摘要

Design issues related to constructing real-time parallel embedded systems are discussed. Our proposed methodology uses software and embedded processors, with off-the-shelf or custom attachments, to achieve performance goals. Custom architectures are constructed by using multiple copies of a core embedded processor linked together with FIFO memories or other communication structures, and augmented with appropriate high speed data manipulation input/output devices. Some field programmability and customization is possible through the use of SRAM program memories.