Efficient SoC Design with Homogeneous Processor Arrays

摘要

In this paper we present two new approaches for efficient system-on-chip (SoC) design with homogeneous processor array for real-time applications. Firstly, a novel systolic array control mechanism based on very long instruction word principles (VLIW), where a single VLIW controls systolic array composed of different PE types is presented. Furthermore, each PE can execute many operations in parallel. Data flows between PEs and parts of systolic array with different types of PEs remain synchronous. Secondly, simultaneous execution of independent algorithm data sets, or even different algorithms, on systolic array termed multithreading on systolic arrays is proposed. This approach results in higher throughput and improved utilization of systolic array composed of pipelined functional units within PEs. Simulation results confirm these claims.