Timing Analysis in a Logic Synthesis Environment

摘要

A goal of a logic synthesis system is the automatic generation of area optimised designs that meet timing requirements. The design process involves repeated timing analyses followed by appropriate modifications. We present fast new algorithms for system level timing analysis and for the generation of timing constraints to guide the re-design of portions of combinational logic. Our systematic approach correctly models designs that incorporate level sensitive latches controlled by multi-frequency, as well as simple multi-phase, clocks. A new feature is that the minimum number of settling times are evaluated for the nodes of combinational networks with input transitions controlled by different clock signals. The computer program Hummingbird uses the algorithms presented. Hummingbird interfaces with other programs in the Berkeley Synthesis System through the OCT data base. For a digital signal processing chip, comprising 3681 standard cells, timing analysis is performed in 14.87 cpu seconds on a VAX 8800 running the ULTRIX operating system.