TIMING CONSTRAINT GENERATING DEVICE OF LOGIC SYNTHESIS, AND LOGIC SYNTHESIZING METHOD AND PROGRAM

摘要

PROBLEM TO BE SOLVED: To generate an RTL (register transfer level) and timing constraints, to unify management and to prevent of the occurrences of errors, such as correction omission and mismatching.;SOLUTION: A constraint generating device 110 is provided with a means which inputs a hardware descriptive sentence from a storing means that stores hardware description (RTL) described in a hardware description language to scan the hardware descriptive sentence, checks whether or not a predetermined keyword exists in a comment field of an input/output terminal declarative statement, extracts a parameter corresponding to the keyword when the keyword exists, and generates from the keyword and the parameter timing constraint information which corresponds to the keyword and is adapted to a syntax format to be used by a logic synthesizer for performing logic synthesis from hardware description, and the logic synthesizer 102 synthesizes logic circuits so as to satisfy the timing constraint information to the hardware description.;COPYRIGHT: (C)2007,JPO&INPIT