A goal of a logic synthesis system is the automatic generation of area optimised designs that meet timing requirements. The design process involves repeated timing analyses followed by appropriate modifications.
We present fast new algorithms for system level timing analysis and for the generation of timing constraints to guide the re-design of portions of combinational logic. Our systematic approach correctly models designs that incorporate level sensitive latches controlled by multi-frequency, as well as simple multi-phase, clocks. A new feature is that the minimum number of settling times are evaluated for the nodes of combinational networks with input transitions controlled by different clock signals.
The computer program Hummingbird uses the algorithms presented. Hummingbird interfaces with other programs in the Berkeley Synthesis System through the OCT data base. For a digital signal processing chip, comprising 3681 standard cells, timing analysis is performed in 14.87 CPU seconds on a VAX 8800 running the ULTRIX operating system.
我们提出了用于系统级时序分析和时序约束生成的快速新算法,以指导组合逻辑各部分的重新设计。我们的系统方法正确地建模了包含由多频率以及简单的多相时钟控制的电平敏感锁存器的设计。一项新功能是评估具有不同时钟信号控制的输入转换的组合网络节点的最小建立时间。 P>
计算机程序Hummingbird使用给出的算法。蜂鸟通过OCT数据库与伯克利综合系统中的其他程序进行交互。对于包含3681个标准单元的数字信号处理芯片,在运行ULTRIX操作系统的VAX 8800上,在14.87 CPU秒内执行了时序分析。 P>
机译:使用时序和逻辑过滤的可感知耦合的静态时序分析中的悲观主义减少
机译:具有逻辑关联的虚假攻击者感知真串扰噪声分析,可进行准确的时序分析
机译:具有逻辑关联的虚假攻击者感知真串扰噪声分析,可进行准确的时序分析
机译:逻辑综合环境中的时序分析
机译:司法进度分析和施工延误索赔中的浮动,逻辑,资源分配和延误时间安排的动态。
机译:注释概念的综合和富集分析:基于逻辑的方法来解释高通量实验
机译:使用定时和逻辑滤波的耦合感知静态时序分析中的悲观减少