Addressing Link Degradation in NoC-Based ULSI Designs

摘要

Process variability makes silicon devices to become increasingly less predictable, forcing chip designers to create different techniques to avoid losing performance and keeping yield. NoC links are also affected from process variation. Actually, the probability of having faulty links in a NoC might considerably increase in future CMP systems, expected to be implemented with 22nm technology by 2015. In this paper we propose a new technique to overcome the presence of failures in NoC links. The proposed mechanism, a variable phit-size NoC architecture, is intended to face both manufacturing defects and variation-induced timing errors. Our new mechanism adapts link operation to the real conditions of the manufactured chip and therefore it is able to keep links working in the presence of variations. Simulation results show that most of the still available bandwidth present in links affected by process variation can be retrieved, thus avoiding the performance degradation that other mechanisms, like reducing link frequency, would introduce.