4th International Workshop on On-Chip Memory Hierarchies and Interconnects (OMHI)

摘要

Current chip multiprocessors (CMPs) include several levels of on-chip caches to avoid the huge latencies of accessing the off-chip DRAM main memory modules. These caches must be efficiently interconnected to avoid performance penalties. On-chip networks are used to interconnect the memory hierarchy inside the processor chip. Latencies can be significantly affected by the devised on-chip memory hierarchy and the interconnect design, whose impact on the overall latency strongly depends on the core count. Consequently, this problem aggravates with the increasing core counts, which is the current commercial trend. By contrast, the main concern in GPUs is on memory bandwidth instead of latencies. Current GPUs are designed to hide memory latencies through fine-grained multithreading. The main goal of on-chip memories in current GPUs is to reduce off-chip memory traffic. In this context, the programmer plays a key role in improving cache access locality. Hence we can conclude that CPUs and GPUs require memory organizations with different characteristics. Thus, as current heterogeneous CPU-GPU systems are proliferating in the market, the memory system must be designed to efficiently support both types of memory organizations: latency-oriented and bandwidth-oriented.