Dept. of Comput. Sci. Eng., Univ. of South Florida, Tampa, FL;
circuit layout CAD; circuit optimisation; crosstalk; high level synthesis; integrated circuit interconnections; integrated circuit noise; integrated logic circuits; iterative methods; network routing; simulated annealing; system-on-chip; Cadence-SOC encounter; DSM regime; DSP benchmarks; bus-based architecture; circuit routing; coupling noise; crosstalk noise minimization; floorplan driven high level synthesis; interconnect density; iterative design flow; macro-cell based design;
机译:动态多电源电压的平面图驱动架构和高级综合算法
机译:平面图驱动的多电压高级综合
机译:平面图驱动的多电压高级综合
机译:PloorPlan在基于宏细胞设计中的串扰噪声最小化的高水平合成
机译:纳米级设计中互连串扰噪声和功耗的最小化
机译:常规胸部计算机断层扫描术中的可行剂量减少:使用最后三代扫描仪来保持恒定的图像质量:从滤波反投影到经国歌会确认的迭代重建以及新型全集成探测器设计的影响可将电子噪声降至最低
机译:性能驱动的可感知平面图的高级综合
机译:基于sma的slat-Cove填料用于气动降噪的分析驱动设计优化