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Concurrent path sensitization in timing analysis

机译:时序分析中的并发路径敏化

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The authors describe a new two-step approach for determining thendelay of the longest statically sensitizable path(s) in a combinationalncircuit. In the first step, the conditions for sensitizing all pathsnwith the same path delay, D, are derived. In the second step, thesenconditions are checked for consistency by a Boolean satisfiabilitynalgorithm. This approach is unique in that it enumerates pathsnimplicitly, giving it a decided performance edge over explicit pathnenumeration methods. The authors describe an implementation of thisnapproach in an experimental timing analysis program, STA, and presentnpreliminary results of its application to a representative set ofnbenchmarks
机译:作者描述了一种新的两步法,用于确定组合电路中最长的静态敏感路径的延迟。在第一步中,得出了用于以相同的路径延迟D激励所有路径n的条件。在第二步中,通过布尔可满足性算法对这些条件进行一致性检查。这种方法的独特之处在于它隐式枚举了路径,从而使它在显式的路径枚举方法上具有确定的性能优势。作者描述了在实验时序分析程序STA中该方法的实现,并介绍了其在代表性基准测试中的初步应用结果。

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