基于锁存器路径的静态时序分析在第三方验证中的应用

摘要

With the expansion of FPGA design scale,STA can relieve the stress of timing simulation,shorten project cycle.The common STA is usually FF_ Based,but after synthesis,unexpected Latch can be generated.The calculating algorithm between Latch_ Based STA and FF_ Based STA is different.In order to achieve a 100％ coverage rate of SAT path analysis,it is necessary for the Independent Verification Authority to do some research on Latch_ Based STA.The conceptions of "Time Borrowed"," Time Given" were explained.The feature of "Latch slack time" was analysed and its function graph was plotted..In order to describe "Timing Loosen" and "Timing Tighten" separately effected by "Time Borrowed" and " Time Given",two separate examples were analysed by Prime Time (a tool of Computer model simulation used for STA).A 100％ coverage rate of STA path analysis was achieved,and the requirement of Independent Verification was satisfied.%随着可编程逻辑门阵列(FPGA)设计规模的扩大,静态时序分析可有效减轻时序仿真的负担,缩短项目周期;常见的静态时序分析(STA)多是基于触发器(FF_ Based STA),对触发器的STA算法研究已经比较成熟;但FPGA综合后网表可能会产生锁存器,而锁存器的STA与触发器的STA在算法上存在差异;为保证在FPGA产品第三方验证工作中对STA路径分析覆盖率达到100％,有必要对基于锁存器的时序分析(Latch_Based STA)做研究;阐述了锁存器“时间借人”与“时间借出”的概念;分析了“锁存器宽裕时间(slack time)”特性,绘制了其函数图;在某FPGA第三方验证项目中使用STA工具Prime Time(一种计算机模型分析工具),分别对由“时间借入”、“时间借出”而导致“时序松弛”和“时序收紧”两种情况做了计算和分析,对STA路径分析覆盖率达到了100％,满足了第三方验证要求.