Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories

摘要

Content addressable memories (CAMs) are commonly used in applications requiring high speed access to some data set. This technology allows data items to be accessed in constant time based on content rather than on address. Unfortunately this technology has several drawbacks: it occupies more die area per bit, dissipates more power, and has higher latency. Recently, an efficient architecture based on a parallel hashing has been proposed as an alternative to CAM technology. In the present paper, we go a step further by backing preliminary simulation results of this proposed architecture by a complete analytical model. The insertion operations applied on the proposed architecture can be modeled with the balls and urns problem. We also propose a method to identify optimal configuration parameters in order to start designing efficiently. Finally, a VLSI implementation and optimizations of the proposed architecture are presented in order to obtain a more thorough understanding of how it could compare to commercial CAMs. Because of its simple design and of the widely spread use of the required tools, this new architecture offers a very appealing alternative to CAM technology.