Spatial and temporal temperature variations in CMOS designs

摘要

Due to the rapid growth in the number of transistors per chip, the power consumption of the average nMOS ASIC reached the level of one Watt, which is, in order of magnitude, about the maximum power consumption allowed for a cheap plastic package without thermal enhancements like drop-in heat spreader, fused leads or exposed pads. The internal chip temperature is the result of the combination of the chip power, the package, a possible heatsink, the application board and the airflow conditions. This requires a reasonably accurate model that includes the thermal properties of the chip, the bonds, the package and the system.