Concatenated Error Correction Code Implementation on FPGA

摘要

The requirements of highly reliable data transmission over interference and noisy channels are imposed on modern radio communication systems. In this connection, forward error correction has become an indispensable step in the digital processing of information data during transmission. Today there are a large number of FEC codes, one of the most popular are low density parity check codes (LDPC). The paper presents the results of the development of the FPGA cascade codec with the internal LDPC code of the DVB-S2 standard and the external Reed-Solomon code. The use of the cascade encoding method allows to get rid of residual errors arising from the decoding of LDPC-code. The developed architectures, methods for increasing productivity and the used FPGA resources are presented.