Implementation of block code Viterbi decoders for high-speed error correction systems.

摘要

The trellis structures of block codes are amenable to high speed CMOS implementation. For a given CMOS process, block code Viterbi decoders enable data rates higher than those achievable using convolution codes and decoders. This increase in speed comes at the expense of a modest reduction in coding gain. Making block codes an attractive choice for satellite trunks and future high-speed communication networks.; However, relatively little research has focused on the implementation of block code Viterbi decoders. Since convolutional decoders, when they can meet system throughput requirements, are typically smaller and use less power than their block code equivalents. But convolutional decoders are pushing the limits of available technology to keep up with the demand for broadband communications. Thus, making block code Viterbi decoders more attractive.; This research effort focuses on the development of a Viterbi decoder for a (64,35) Reed-Muller subcode. Taking advantage of its trellis properties to implement a concurrent bi-directional Viterbi decoder. This decoder, the RMS6435, is also to be used in a (64,40) Reed-Muller decoder as a high-speed replacement for the (2,1,6) convolutional code used in many concatenated coding systems.; Block code Viterbi decoders require new synchronization algorithms. Using existing synchronization algorithms developed for convolutional codes as a model, we have identified and implemented an effective synchronization detector. While the initial results are promising, there are a few issues that require additional research.