Development of parallelism for circuit simulation by tearing

摘要

A hierarchical clustering with min-cut exchange method fornparallel circuit simulation is presented. Partitioning into subcircuitsnis near optimum in terms of distribution of computational cost and doesnnot sacrifice the sparsity of the entire matrix. In order to compute thenarising dense interconnection matrix in parallel, multilevel andndistributed row-base dissection algorithms are used. A processing speednup of 28 with 64 processors was achieved in large scale DRAM simulations