首页> 外文会议>Systems, Man and Cybernetics, 1992 >A digital phase locked loop for power conversion ASICs
【24h】

A digital phase locked loop for power conversion ASICs

机译:用于电源转换ASIC的数字锁相环

获取原文
获取原文并翻译 | 示例

摘要

It is shown that a digital phase locked loop can be designed tonperform the functions of capturing fundamental of an input referencenwave, and producing sine and cosine values of the phase angle to a 16nbit accuracy. Digital differential analyzers are used for continuousncalculation of the sine and cosine, since the simplicity of the hardwarenrequired reduces the number of cells needed for implementation in a gatenarray ASIC. In the implementation the variable frequency oscillatornoccupies 2586 cells the phase comparator 2711 cells, PI control 1196ncells, and compensating filters in the loop a total of 3018 cells.nAlternative methods would have required a significantly greater area, ornplaced an additional software burden on an existing processor. While thendevice is currently being incorporated into a power converter chip aimednat center frequencies of 40-60 Hz, with a lock band of ±8 Hz anwider frequency range is possible with a sacrifice of some accuracy innthe output values. A version for motor current control over a frequencynrange from 0-2000 Hz is being developed
机译:结果表明,可以设计数字锁相环来实现捕获输入参考波的基波并产生相位角的正弦和余弦值至16nbit精度的功能。数字差分分析仪用于正弦和余弦的连续计算,因为所需硬件的简单性减少了在门阵列ASIC中实现所需的单元数量。在实施中,可变频率振荡器占用2586个单元,相位比较器2711个单元,PI控制1196n个单元,以及环路中的补偿滤波器,总共3018个单元。n其他方法将需要更大的面积,或者给现有处理器增加了额外的软件负担。当时,该设备目前正在以40-60 Hz的中心频率为目标的功率转换器芯片中,但在±8 Hz的锁定频带内,可以在更宽的频率范围内牺牲输出值的一些精度。正在开发一种用于在0-2000 Hz的频率范围内进行电动机电流控制的版本

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号