A novel approach to cost-effective estimate of power dissipation inCMOS ICs

摘要

An approach to the estimate of power dissipation in CMOS ICs basednon the current limited model of MOS transistors able to accuratelynevaluate current waveforms for all types of digital circuits isnpresented. The efficiency of the tool developed is such that ICs with upnto 10⁴-10⁵ transistors can be cost-effectivelyntreated without any need of arbitrary partitioning. In addition, thenalgorithm can be used to study problems related to excessive values ofnsupply currents, such as electromigration or noise, and voltage drops onnpower buses. Results obtained with significant benchmarks are shown innorder to demonstrate the accuracy and the efficiency of the proposednmethod