A 0.4μ m 1.4ns 32b Dynamic Adder using Non-precharge Multiplexers and Reduced Precharge Voltage Technique

摘要

This paper describes fast 32-bit dynamic adder using non-precharge multiplexers and reduced precharge voltage technique. Design adopting novel multiplexers reduces transistor count, resulting in the reduction of total parasitic capacitance. Reduced precharge voltage makes the discharge time shorter. Experimental circuit has been fabricated using 0.4μm CMOS technology and we confirmed the delay of 1.4ns at the supply voltage of 3.3V at room temperature.