Amorphous Silicon Vertical Thin Film Transistor for High Density Integration

摘要

This paper presents a fabrication process for vertical thin film transistors (VTFT) based on hydrogenated amorphous silicon (a-Si:H) technology. This process yields VTFTs with an ON/OFF ratio of 10~5 and a leakage current of the order of 10~(-13)A for a channel length of 1 μm. The device structure, because of significant undercutting formed after dry-etch process (reactive ion etching or RIE), has a channel profile that is skewed as opposed to vertical. This serves to compromise the structural integrity and the electrical performance of the device. Therefore, an anisotropic dry-etch process for this channel profile is being developed. It is found that a CF_4/20%H_2 gas mixture yields a sharp vertical sidewall profile. In addition, a modified masking process has been developed to produce a rectangular photoresist profile so as to achieve an anisotropic etch profile for the channel region. The effects of the photoresist geometry on the anisotropic dry-etch process will be discussed.