An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS

摘要

Injection locking is an effective method to reduce the jitter of clock generators especially for a ring oscillator-based PLL that has poor phase noise. While the use of injection locking reduces the output jitter, one disadvantage is that the output frequency can be changed only by integer multiples of the reference frequency, if it can be changed at all. In this work, an ADPLL-based clock generator is presented that employs a fractional-injection-locking method that exploits the multiphase output of a ring oscillator. The clock generator achieves an average of 4.23 ps_rms jitter and a frequency resolution of 1MHz while using a reference clock of 32MHz.