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A counter-based all-digital spread-spectrum clock generator with high EMI reduction in 65nm CMOS

机译:基于计数器的全数字扩频时钟发生器,可在65nm CMOS中大幅降低EMI

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References(6) An all-digital spread-spectrum clock generator (ADSSCG) with direct modulation on the digitally controlled oscillator (DCO) is presented. The proposed ADSSCG can generate an accurate triangular modulation on the output frequency, and thus it can achieve high electromagnetic interference (EMI) reduction with a smaller spreading ratio as compared with existing designs. In addition, the proposed frequency counter-based mechanism can maintain the long-term frequency stability of the ADSSCG. The proposed ADSSCG is implemented in a standard performance 65nm CMOS process, the active area is 85μm × 85μm. It consumes 163.9μW at 270MHz with a 1.0V power supply. The EMI reduction of the proposed ADSSCG is 13.99dB with a 0.5% spreading ratio at 270MHz, and 20.23dB EMI reduction is achieved with a 1.5% spreading ratio at 162MHz. Moreover, the proposed ADSSCG is designed with standard cells, and thus it can be ported to different process in a short time.
机译:参考文献(6)提出了一种在数字控制振荡器(DCO)上具有直接调制功能的全数字扩频时钟发生器(ADSSCG)。提出的ADSSCG可以在输出频率上生成精确的三角调制,因此与现有设计相比,它可以以较小的扩展比实现高电磁干扰(EMI)降低。此外,所提出的基于频率计数器的机制可以保持ADSSCG的长期频率稳定性。拟议的ADSSCG采用标准性能65nm CMOS工艺实现,有效面积为85μm×85μm。使用1.0V电源时,它在270MHz时消耗163.9μW。所提出的ADSSCG的EMI降低为13.99dB,在270MHz时扩展率为0.5%,而EMI降低了20.23dB,在162MHz时扩展率为1.5%。而且,所提出的ADSSCG是用标准单元设计的,因此可以在短时间内移植到不同的过程。

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